1. Field of the Invention
The embodiments herein generally relate to integrated circuit structures and, more specifically to transistor structures that include asymmetric stressing structures within source and drain regions of the transistor.
2. Description of the Related Art
Many recent advances have been achieved within integrated circuit transistors by forming the transistors to be asymmetric. For example, two recent U.S. Patent Publications 2009/0020830 entitled Asymmetric Field Effect Transistor Structure And Method and 2008/0290422 entitled Asymmetric Field Effect Transistors (FETs) (both of which are incorporated herein by reference) disclose numerous advantages for making transistors asymmetric in design. For example, with asymmetric transistors, both series resistance in the source region and gate to drain capacitance are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay). Specifically, different heights of the source and drain regions and/or different distances between the source and drain regions and the gate can be tailored to minimize series resistance in the source region (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and to simultaneously minimize gate to drain capacitance (i.e., in order to simultaneously ensure that gate to drain capacitance is less than a predetermined capacitance value).
The embodiments disclosed below provide different methods and structures that provide additional benefits of asymmetric transistors.